Digital modulation technology is one of the key technologies of the high-speed communication transmission system. In this article, an architecture of high-speed digital modulation signal generation in parallel is proposed, which can be implemented by algorithm-level pipeline in field programmable gate array (FPGA) hardware platform. With theoretical analysis and derivation, DFT/ IDFT in parallel frequency domain forming filter can be cascaded by two levels of the low-complexity based-8 FFT algorithm, and the specific FPGA architecture and implementation method are given. In addition, a mixing-free digital orthogonal up-conversion architecture suitable for parallel implementation is analyzed and designed to further reduce hardware resource. The simulation experiments evaluate the algorithm of the high-speed parallel digital modulation architecture, and the FPGA hardware implementation results test the spectrum performance of the high-speed parallel digital modulation signal.