In nanoscale semiconductor manufacturing processes, the operating voltage of chips has been reduced to as low as 0.8 V, while the power consumption of some chips exceeds 700 W and the peak current exceeds 2 000 A. These trends impose stringent requirements on the power distribution network (PDN) that supports chip operation, including wide frequency bandwidth, ultra-low impedance, and low power loss. The intrinsic parameters of decoupling capacitors within the PDN are critical to its optimal design. To obtain accurate capacitor parameter models for PDN power integrity simulation and analysis, this paper proposes a high-precision broadband method for extracting the intrinsic parameters of decoupling capacitors based on a vector network analyzer (VNA). Vector fitting and error correction techniques are introduced to address the zero-crossing issue in test trajectories caused by trace noise, and the intrinsic parameters of the decoupling capacitors are extracted. An experimental system is constructed, with fixtures designed and multi-stage calibration and fixture de-embedding implemented. The test frequency range is 500 Hz to 3 GHz, achieving a capacitance error of ≤5%, an equivalent series resistance (ESR) error of ≤3%, and an equivalent series inductance (ESL) error of ≤6%. The measured intrinsic parameters of the decoupling capacitors are consistent with the reference values, and the impedance curves derived from substituting these parameters into the equivalent model align with the measured results. This method enables efficient and reliable extraction of the intrinsic parameters of decoupling capacitors, providing robust data for the optimal design of PDN and holding significant engineering value for the development of power supply systems supporting computing networks and digital systems.