The analog time-register-based time-domain signal processing circuit (refer as analog time-domain circuits for short) is a current research hotspot, featuring lots of merits such as low power consumption and strong anti-interference ability. However, it suffers the time register-overflowing issue. This paper proposes and verifies an automatic calibration circuit that can effectively solve the problem of time register overflow caused by process-voltage-temperature (PVT) variations in analog time-domain circuits. The circuit mainly consists of a time register, a digital control algorithm, a time error detector, and a programmable current source. By using the digital control algorithm in combination with the time error detector, it can detect in real time whether the time register is at risk of overflow. When an overflow risk is detected, it will adaptively modify the programmable bias current to adjust the capacitor discharging speed in the time register therefore eliminate the risk. The calibration circuit is designed and fabricated using the SMIC 0.18 μm CMOS process. The chip test results show that, without using this calibration circuit, when the temperature and power supply voltage fluctuate, the time register bears the overflowing risk and a time deviation of the analog time-domain signal greater than 15% is observed. When using this calibration circuit, the time register runs stably, and the time deviation is less than 1%. This design can be integrated into kinds of analog time-domain signal processing circuits such as time-to-digital converters and all-digital phase-locked loops, to enhance their robustness.