With the continuous advancement of chip technology and the increasing frequency of chip design, delay faults have become an important factor leading to the failure of high-speed chips. In the post-silicon validation stage, due to the lack of a method for measuring the global path delay of chips, the traditional method of constructing delay measurement circuits can only obtain the delay variation of specific critical paths, and comprehensive path delay analysis cannot be conducted when the chip fails. This paper proposes a frequency sweeping at-speed testing method based on scan chains to measure the delay of a large number of timing paths inside the chip and obtain the timing margin. Addressing the issues of long test vector generation time and reliance on specialized testing equipment, frequency sweeping at-speed testing was successfully implemented on a self-developed hardware platform through the generation of multi-frequency test vectors and an improved data verification algorithm. The measurement error of the chip’s path delay is around 8 ps. Experimental verification on different chips at different temperatures confirmed the effectiveness of this method in characterizing path delay, providing a fast and effective method for future research on environmental adaptability analysis and lifetime prediction of high-speed chips through delay parameters.