With the improvement of the manufacturing process, static power consumption has gradually become one of the main power consumption sources of routers. Aiming at the high power consumption of multi-core systems based on the on-chip network architecture, this paper proposes a power gating strategy based on packet classification, and modifies the router architecture. In this scheme, first classify data packets, and then use bypass to perform different processing on classified data packets to bypass the dormant router, thereby reducing the extra data packet delay and power consumption caused by the application of power gating. Bypass can ensure the transmission of data packets when the router is sleeping, increase the sleep time of the sleeping router, and reduce static power consumption. The classification of data packets makes the sleep and wake-up of the router more reasonable and efficient. The simulation results show that the solution in this paper can significantly reduce the static power consumption of the router and the delay of the network. Compared with the traditional power gating technology, it can reduce the static power consumption by 72. 4% and the average packet delay by 16. 8%; compared with the classic power gate, the controlled bypass router reduces the static power consumption by 12. 4% and the average packet delay by 4. 7%. The additional hardware overhead of the router has only increased by 3. 2%.