Time-to-digital converter (TDC) is a time interval measurement circuit, widely used in time-of-flight (ToF) measurement, frequency measurement and other fields. Aiming at the problem that traditional TDC was constrained by the mutual restriction of resolution and measurement range, a novel TDC with two-step quantization that gave consideration to both resolution and measurement range was designed in SMIC 55 nm CMOS process. The first stage used ring structure for coarse quantization, which improved the measurement range. The second stage used a delay locked loop (DLL) to generate the control voltage that voltage-controlled delay cells needed and improved the resolution by scaling the load capacitors of the delay cells. This paper proposed a simple algorithm of time residue generation that transmitted the time interval cannot be quantified in first stage to second stage. The delay cell structure in first stage was designed in order to eliminate the delay mismatch that multiplexer caused when signal circling. The simulation results showed that the proposed TDC could realize the resolution of 4. 8 ps, the measurement range of 1. 26 μs. The measured maximum differential non-linearity (DNL) is 0. 6 LSB. The measured maximum integral non-linearity (INL) is 1. 8 LSB.