For the low implementation complexity requirement of the low-density parity-check ( LDPC) encoders in consultative committee for space data systems (CCSDS) standard, an implementation architecture of multi-channel parallel encoder is proposed for LDPC codes with different code lengths and code rates. The matrix information can be shared among all parallel computing units to improve resource utilization by repeatedly utilizing the storage unit in the encoder. Furthermore, the single-channel and multi-channel encoders with code rates of 1 / 2, 2 / 3 and 4 / 5 are verified and tested on the field programmable gate array (FPGA) hardware platform. The test results show that the throughput of the encoders adopting the multi-channel parallel coding scheme is higher than that of the single-channel encoders and achieves more than 1Gbps. The resources of the look-up table for the multi-channel encoders are reduced by 40%, 44% and 46%, respectively, compared with the single-channel encoders with multiple groups that achieves approximately the same throughput. By making full use of the storage resources in FPGA, this architecture can reduce the complexity of hardware implementation effectively.