面向FPGA部署的航磁补偿加速器架构设计
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1.中国科学院空天信息创新研究院北京100190;2.中国科学院大学电子电气与通信工程学院北京100049

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TN492;TP212.1

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中国科学院战略性先导科技专项(B)(XDB1110401)资助


Design of an aeromagnetic compensation accelerator architecture for FPGA deployment
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1.Aerospace Information Research Institute, Chinese Academy of Sciences, Beijing 100190, China; 2.School of Electronic, Electrical and Communication Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

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    摘要:

    在航磁测量中,磁信息的质量需要高精度的数据处理与实时性保障。针对现有基于通用处理器的软件补偿系统在嵌入式平台中存在计算延迟大且时序不可预测,难以满足无人机等载荷受限平台对实时性与确定性的严苛要求等问题,提出一种针对托尔斯-劳森(Tolles-Lawson, TL)模型的现场可编程门阵列(field-programmable gate array, FPGA)硬件加速架构。通过对TL模型信息行向量进行面向硬件的代数重构,在Xilinx Artix-7平台上设计并对比了“全并行流水”与“分时复用”两种处理架构计算效果。实验结果表明,全并行架构将单次补偿延迟压缩至540 ns,但需消耗132个数字信号处理器(digital signal processor, DSP);而分时复用架构通过浮点单元共享,仅占用9个DSP与7 273个查找表(look-up table, LUT),在6.1 μs的延迟下实现了逾90%的DSP资源节约率。基于Cessna 208飞行平台的实测数据验证显示,该系统的补偿改善比最高达14.8,磁干扰信号标准差从364.5 pT降至24.7 pT。相比于通用处理器的软件实现,该硬件架构在保持补偿精度基本相当的前提下,计算效率提升了1~2个数量级。该设计有效解决了高精度磁补偿算法在低功耗硬件上的部署问题,实现了高精度、强实时、强确定性的机载航磁在线补偿,为无人机及轻型航空器等平台的航磁系统提供了一种低成本、工程可落地的实现方案。

    Abstract:

    In aeromagnetic surveys, the quality of magnetic information requires high-precision data processing and real-time assurance. Aiming at the problems that existing software compensation systems based on general-purpose processors suffer from high calculation latency and unpredictable timing on embedded platforms, making it difficult to meet the strict requirements for real-time performance and determinism of payload-constrained platforms such as unmanned aerial vehicles (UAVs), this paper proposes an FPGA hardware acceleration architecture for the Tolles-Lawson (TL) model. By performing hardware-oriented algebraic reconstruction on the TL model information row vectors, two processing architectures, namely “fully parallel pipelining” and “timedivision multiplexing,” were designed and compared on the Xilinx Artix-7 platform. Experimental results indicate that the fully parallel architecture compresses the single compensation latency to 540 ns but consumes 132 digital signal processing (DSP) slices; whereas the time-division multiplexing architecture, through floating-point unit sharing, occupies only 9 DSPs and 7273 look-up tables (LUTs), achieving over 90% DSP resource saving rate with a latency of 6.1 μs. Measured data validation based on the Cessna 208 flight platform shows that the compensation improvement ratio of the system reaches up to 14.8, and the standard deviation of magnetic interference signals decreases from 364.5 pT to 24.7 pT. Compared with software implementations on general-purpose processors, this hardware architecture improves calculation efficiency by 1-2 orders of magnitude while maintaining basically equivalent compensation precision. This design effectively solves the deployment problem of high-precision magnetic compensation algorithms on low-power hardware, realizes airborne aeromagnetic online compensation with high precision, strong real-time performance, and strong determinism, and provides a low-cost and engineering-feasible implementation scheme for aeromagnetic systems on platforms such as UAVs and light aircraft.

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邓智瀚,蔡浩原,刘晓东,陈骏彬,朱万华.面向FPGA部署的航磁补偿加速器架构设计[J].电子测量与仪器学报,2026,40(7):268-279

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