The core of AC parameter testing lies in chip delay measurement, with the continuous scaling of semiconductor processes and exponential growth of circuit complexity, even minor delay defects can now induce critical timing failures. The necessitates implementing high-precision dynamic parameter testing schemes on automatic test equipment (ATE). To address this requirement, a hybrid FPGA-based measurement architecture has been proposed: A dynamic selection unit combining timing logic control and combinational logic achieves high-precision, high flexibility signal capture. With a three-chain time-to-digital converter (TDC) based on Nutt interpolation methodology, incorporating a phase-shifted-clock-calibrated coarse measurement arbitration module and a CARRY4-cascaded fine measurement module. Significant errors in coarse measurement data induced by metastability phenomena within asynchronous circuits were eliminated through this structural configuration, while versatile compatibility with multiple measurement scenarios was preserved. Dynamic parameter quantification capabilities encompassing rise/fall time, pulse width, transmission delay, and frequency were achieved by synergistic interactions between the selection unit and TDC core, achieving concurrent nanosecond-level measurement velocity and picosecond-level resolution. The TDC resolution achieved on Kintex-7 is 12.019 ps, with a differential nonlinearity (DNL) of ［-0.80 LSB,4.67 LSB］, an integral nonlinearity (INL) of ［-3.82 LSB,5.02 LSB］, and a root-mean-square accuracy of 23.363 ps. Functional verification under practical measurement conditions and stability assessment protocols were implemented, with operational robustness in real-world applications being conclusively demonstrated.