A low power, small die size 14bit 125 MSPS pipelined ADC is presented. Switched capacitor pipelined ADC architecture is chosen for the 14bit ADC. In order to achieve low power and compact die size, the sample and hold amplifier is removed, the 4.5bit substage circuit is used in the first pipelined stage. The capacitor down scaling technique is introduced, and the current mode serial transmitter is used. A modified miller compensation technique is used in the operation amplifiers in the pipelined substage circuits, which offers a large bandwidth without additional current consumption. A 1.75 Gbps transmitter is introduced to drive the digital output code, which only needs 2 output pins. The ADC is fabricated in 0.18 μm 1.8 V 1P5M CMOS technology. The test results show that the 14bit 125 MSPS ADC achieves the SNR of 72.5 dBFS and SFDR of 83.1 dB, with 10.1 MHz input at full sampling speed, while consumes the power consumption of 241 mW and occupies an area of 1.3 mm×4 mm.