With the development of integrated circuit technology and increased integration, circuit delay has significantly decreased. The research on traditional time-to-digital converters (TDC) tends to focus on circuit designs that combine high resolution and high accuracy. In recent years, as Moore’ s law has gradually become less effective and with the rise of the Internet of Things ( IoT), lightweight, miniaturized, and low-power edge devices have rapidly developed. The research focus on miniaturized TDCs for on-chip delay measurement has gradually shifted towards high-precision and low-power designs. Based on the Xilinx Virtex-6 XC6VLX240T FPGA development platform, a coarse measurement structure using a self-timed ring ( STR) instead of direct counting method and a fine measurement structure consisting of two symmetrical delay chains are proposed. The coarse measurement structure’ s STR is combined with the fine measurement’s symmetrical delay chains using edge coincidence detection units and latch units. The design results show that the range of the structure can reach 491 ns, with a resolution of 14. 8 ps and a maximum accuracy of 12. 9 ps. The power consumption is 0. 068 W, indicating that the proposed two-stage differential structure has the characteristics of high precision and low power consumption.