At present, long test time and low test efficiency are one of the key problems affecting test cost in IC testing. To solve this problem, a test set reordering method based on test performance estimation is proposed. Firstly, different fault types are classified and modeled, and then each fault type is simulated. The test performance of test patterns is estimated by injecting faults into each logic gate and counting the total area of test patterns hitting the fault gate. Finally, the test sets are reordered according to the test performance. Experiments show that the sequenced test set test can reduce the fault detection time by 5329% for single stuckat fault. This method is to analyze and count the logic structure of the circuit and then optimize the test set, test the ISCAS 89 standard circuit, and compare it with other test sets to reorder it, which has obvious optimization. The algorithm operation is completely softwarebased, without any additional hardware overhead, and can be directly compatible with the traditional integrated circuit test process.