A 625 MS/s, 12 bit twochannel time interleaved ADC is designed in 40nm CMOS process. The single channel is pipeline ADC with no sampleandholdamplifier (SHA) frontend for lowpower consumption. A wideband and highlinearity foreground input buffer and a high speed and high precision bootstrapped switch are used for ensuring the effective input bandwidth of the interleaved system. A background calibration algorithm based on reference channel is applied for sampling time mismatch calibration between channels. This background calibration method is appropriate for completely random input signals. The core area of the system is 069 mm2. The postsimulation results show that the 625 MS/s, 12 bit time interleaved ADC achieves 67 dB of SFDR and 585 dB of SNDR with the Nyquist sampling at full sampling speed, while its power consumption is 295 mW, which meets the design targets and confirms the effectiveness of the design.