In order to evaluate the fault coverage in VLSI accurately, a new logic fault modeling and simulation method is proposed in this paper. Firstly, the circuitlevel faults are injected into the logic cells by simulation and experiments, and the fault dictionary consisted of MTTs is built by analyzing the experimental data. Secondly, an effective testing coverage model is proposed based on the MTTs and their weights, which are then applied to the gatelevel fault simulation. At Last, the proposed method is proved on several combinational benchmark circuits. The results show that, comparing to the traditional stackat fault model, the proposed method can better reflect the fault coverage capability of a given testing set.