Spatio-temporal graph convolutional network (STGCN) enhances the accuracy of traffic speed prediction by capturing the spatial dependencies and temporal dependencies in traffic data through graph convolution and time convolution. However, the hardware implementation of traffic speed prediction using STGCN faces challenges such as high computational demands that do not meet the real-time requirements of practical applications and high resource consumption leading to increased costs. To optimize the traffic speed prediction STGCN model, a method for optimizing the FPGA implementation structure combination of traffic speed prediction STGCN is proposed. Initially, the model is optimized through lightweight pruning and precise selection of prediction data bit-width to reduce computational complexity and resource consumption, verified by Python simulation for feasibility. Subsequently, an optimization strategy using pipeline, parallel computing, and alternating data stream storage is introduced to enhance system computational speed. Finally, the traffic speed prediction STGCN is implemented and tested on FPGA using Verilog programming. Experiments with the PeMSD7(M) dataset show that the FPGA implementation reduces the time for single data traffic speed prediction to 355.5 μs, maximum processing speed increases of 25.9×, 6.7× and 3.5× compared to CPU, GPU platform and FPGA design option 1 comparisons, respectively, proving that the proposed method significantly improves processing speed while maintaining prediction accuracy.