In order to further improve the compatibility of machine vision systems and enrich the types of video formats processed by encoding and decoding systems, a multi interface video encoding and decoding system based on FPGA was designed. By using the asynchronous DDR read-write principle to build the codec selection module and complete the conversion operation of different video formats, the final system supports the decoding of PAL, HDMI and Cameralink videos as well as the encoding functions of HDMI, Cameralink and LVDS videos. Meanwhile, by comparing the transmission characteristics of different video interfaces, the seamless conversion between the above video interface standards is realized. The system can not only be used as an independent video codec system, but also can be connected to ARM processor through LVDS interface, thus expanding its application scenarios. Experimental results show that the system can accurately decode PAL video with a resolution of 720×576, Cameralink video with a resolution of 640×512 and HDMI video with a resolution of 1 080p, and then output it through HDMI, Cameralink and LVDS video interfaces respectively. In addition, the consumption of all kinds of resources in the system does not exceed 50%, which ensures the efficient operation of the system.