With the continuous development of VLSI circuits, the design of the on-chip power delivery network is becoming increasingly important, and the performance of the design needs to be reflected by calculating the quiescent voltage drop of the power delivery network. However, traditional computational methods are time-consuming, resulting in longer chip design cycles. In order to shorten the cycle of chip design and improve the efficiency of chip design, this paper proposes a fast static voltage drop prediction model based on convolutional neural network—ResCSP-34. The model adopts the encoderdecoder structure, firstly the residual network ResNet34 is modified as the main structure of the encoder, then the feature fusion module is introduced into the decoder, and the attention mechanism module is introduced at the connection of the encoder and the decoder, and finally a loss function combining the mean square error, Pearson correlation coefficient and mean absolute error is proposed to train the model. Experimental results show that on the CircuitNet dataset, the average absolute error of the model prediction results is 0.7 mV, which is less than 1 mV, the average value of the Pearson correlation coefficient is greater than 0.93, close to 1, and the average total time for static voltage drop prediction for an on-chip power supply network design is 7.36 s, and the average inference time of the convolutional neural network is 0.015 s. Experimental results show that the ResCSP-34 model can quickly and accurately predict the quiescent voltage drop.