Design of a high current and high power supply rejection ratio LDO using loop isolation
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1.School of Integrated Circuits, Nanjing University of Information Science and Technology,Nanjing 210044, China; 2.Jiangsu Collaborative Innovation Center on Atmospheric Environment and Equipment Technology, Nanjing University of Information Science and Technology, Nanjing 210044, China

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TN43

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    Abstract:

    In view of the problems of low driving capability and high output ripple in traditional LDO with charge pump and NMOS as power transistor, a high-current LDO with isolated AC-DC loops was designed based on Huahong 0.35 μm BCD process. The demand for charge pump driving capability in this LDO is reduced by isolating the DC loop and AC loop, thereby ensuring low ripple in the gate driving voltage of the NMOS power transistor and achieve high current output. The PSRR of LDO is enhanced by adding ripple current absorbing circuit. The results show that in the input voltage range of 3.41~5.5 V, the output voltage of LDO is 3.3 V and the output current can reach 3 A. The PSRR of LDO under light load is 111.261 dB@DC, 86.900 5 dB@1 kHz, 78.947 2 dB@1 MHz. The PSRR under heavy load is 111.280 dB@DC, 84.123 1 dB@1 kHz, 39.263 8 dB@1 MHz.

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  • Received:
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  • Online: April 30,2024
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