In a high-speed satellite data transmission system, factors such as the Doppler effect will cause symbol timing offset between transmitter and receiver, it can be effectively corrected by the Gardner clock recovery algorithm. However, the existing implemental structure of clock recovery algorithm has disadvantages of high sampling rate and complexity, it is difficult to meet the requirements of higher symbol rate and timing offset tolerance because of limited sampling rate and hardware resources in the real-time system. Thus, this paper proposes a new parallel structure based on the Gardner clock recovery algorithm. By introducing add/delete state machine, sample adjusts module, and symbol extract module, it can realize fast symbol timing estimation when sampling at twice the symbol rate. Simulation and FPGA board-level tests show that this structure is suitable for multiple modulation formats of QPSK/8PSK/16APSK. It can tolerate timing frequency offset of up to ±400×10-6, and has a stable bit error rate in long-term tests. In addition, when implementing a real-time receiver system with 625 MBaud symbol rate, the parallel structure proposed in this paper saves about 37% of LUT resources and more than half of the Register and DSP resources compared with the traditional structure. It is practical and has great value in a real-time communication system with limited resources.