In order to reduce the cost and risk of current integrated circuit electromagnetic interference test experiment, an interference generating circuit which can periodically disturb the power supply end of low impedance integrated circuit chip is proposed. The circuit uses low impedance MOS tubes as the output driver, connects multiple MOS tubes to power chips with different output voltage values, and uses FPGA to control the switches of these MOS tubes, which can produce periodic disturbance waveforms with certain frequency and amplitude. The jammer made of the circuit structure can be inserted into the test board in the form of board card and can be powered by ordinary charger. Compared with large equipment such as RF signal source and power amplifier, it has the characteristics of small volume, low power consumption, simple operation, low cost, safety and convenience. The jammer is connected to the load circuit of the chip to be tested with equivalent low impedance for electromagnetic interference test. The test results show that the jammer can generate about 1V voltage disturbance in the range of 0 ~ 30MHz and 0.5V ~ 1V voltage disturbance in the range of 30MHz ~ 80MHz for low impedance load with capacitance of 50pF and resistance of 10 Ω.