To improve the decoding performance, based on the (8176, 7154) LDPC code applied to near-earth space in CCSDS standard, and according to the normalized minimum sum (NMS) decoding algorithm, design and implement the LDPC decoder. The design of the decoder mainly optimized the quantization data of check nodes, the scale factor changes with the number of iterations, and the scale factor value is based on the multiple of 2 and used the right shift addition to replace the multiplication of check node data and scale factor, which simplifies the hardware implementation. In addition, add a decoding verification module to test whether the codeword is successfully decoded after iterative calculation of the check node and the variable node, and the data is sent out after successful decoding or reaching the set maximum number of iterations. The LDPC decoder is designed and implemented based on FPGA. In the hardware design, used parallel decoding circuits to make rational use of hardware resources. When the signal-to-noise ratio is 1.8 and the maximum number of iterations is 15, through simulation and board-level verification, and comparing the decoding results when the scale factor value is 0.5, 0.75 and the scale factor is variable, it is proved that the variable scale factor NMS decoding algorithm can realize the decoding function and has good decoding performance.