NAND FLASH error correcting coding scheme and implementation based on FPGA
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National Key Laboratory for Electronic Measurement Technology, North University of China, Taiyuan 030051,China

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TP333.5

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    Abstract:

    In order to solve the problem of error codes in the process of reading and writing NAND FLASH memory data, an FPGA-based NAND FLASH error correction coding scheme is proposed. The solution uses Micron’s MT29F64G08ABAAA memory chip and is controlled by the FPGA controller for data storage. Every 64Bytes generates 18bits Hamming code check code, and writes the Hamming code check code in FLASH and the Hamming code check code generated when reading the data. The code comparison can determine the position where the error code occurs, and the error code can be corrected by inverting the data bit. The test results show that if the error correction coding scheme is not used for writing and reading 8GBytes data, there are errors in the test at high and low temperatures and normal temperature. The error correction coding scheme is tested at 20℃, 60℃ and -40℃. Error-free, realizes the function of NAND FLASH error correction, and improves the accuracy and stability of data storage.

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  • Received:
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  • Online: August 26,2024
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