In order to meet the realtime requirements, an intraprediction parallel design architecture based on field programmable gate array (FPGA) is proposed. Through the parallel architecture to reduce the operation latency, through the lookup table to simplify the reference pixel selection process, through the prediction unit to reduce the computation and hardware implementation complexity. The experiment code is written in Verilog HDL, simulated with Modelsim SE 10.1a, and integrated on the Xilinx Virtex6 XC6VLX760 FPGA. The results show that the prediction of the 32×32 block requires 570 clock cycles. At 100 MHz clock frequency, the video frame sequence with 60 f/s (frame/s) and resolution of 1 920×1 080 can be encoded in real time.