proposed a method of Multichannel FIFO with mass storage facility based on FPGA.In the highspeed sample board,the speed and capability of the system depend on the FIFO. In order to fulfil highspeed sample board requirements highspeed, huge facility and little volume, slected SDRAM and FPGA to accomplish. The SDRAM has highspeed, huge capability and lowcost but complex. Taking the advantage of FPGA to make up the complexity of SDRAM. , use the FPGA to make the logic of the FIFO, accomplished the SDRAM state controller FIFO address management and FIFO Interface logic. Then accomplish simulation on the Modelsim with a SDRAM model designed by Micron Technolog. At last,applying this method on a PXI board. Analysed the influence of clock frequency, delay parameter and readwrite Frequency to Bit Error, then gived the rectify solution. Realized eight channel FIFO with 16 M storage deep, asynchronous dualport, 16 bits wide and a speed of 128 Mbps.Providing a reliable data storage platform for the high speed data acquisition system.