This paper offers a way to find the best selection of synchronous buck converter switching bridge topology and equipment in the selection of CMOS technology. It is assumed that the DCDC converter is on the same integrated circuit where the load has a constant operating point that is known. The design space consists of the variety of cascode/noncascode switch bridge topologies and available MOS switch devices. The goal of maximizing the power efficiency η is met with a very large design space. To avoid exhaustive simulations, the proposed technologyindependent approximation method narrows down the design space and suggests the most powerefficient combination. Synchronous 3.3~1.65 V Buck converters simulations with core, I/O, and HV devices in 45 and 65nm CMOS technologies confirmed that the method produces reliable comparative results. Furthermore, the outcome is a sharp focus for subsequent detailed dcdc converter design and topologydependent optimization.